debug
{'doi': '10.1049/el.2016.1111', 'member_id': '265', 'member': 'Institution of Engineering and Technology (IET)', 'container-title': 'Electronics Letters', 'primary-resource': 'https://onlinelibrary.wiley.com/doi/10.1049/el.2016.1111', 'tld': 'wiley.com', 'clearbit-logo': 'https://logo.clearbit.com/wiley.com', 'coaccess': [], 'multiple-resolution': [], 'type': 'JOURNAL ARTICLE', 'published_date': 'October 2016', 'publication': 'Electronics Letters', 'supplementary_ids': '10.1049/el.2016.1111', 'title': 'High performance DRAM architecture with split row buffer', 'name': None, 'id': None, 'location': None, 'display_doi': 'https://doi.org/10.1049/el.2016.1111', 'grant_info': None, 'editors': None, 'authors': 'M.‐K. Lee | K.‐S. Chung', 'chairs': None}
https://doi.org/10.1049/el.2016.1111
JSON
XML
Total 29 GB
used 11 GB
Free 16 GB